Exemplary embodiments relate to a regulator circuit and a semiconductor memory device including the same and, more particularly, to a regulator circuit and a semiconductor memory device including the same, which are capable of reducing current consumption by stabilizing a voltage level.
FIG. 1 is a voltage waveform graph showing the waveforms of selected and unselected word lines Sel WL, Unsel WL among the word lines connected to memory cells in a semiconductor memory device when program and verification operations are performed.
Referring to FIG. 1, during a program operation, a program voltage Vpgm and a pass voltage VPASS are supplied to the appropriate ones of the selected and unselected word lines Sel WL, Unsel WL. The program voltage Vpgm is a high voltage (of about 20 V) and higher than the pass voltage. That is, a program voltage Vpgm of about 20 V or higher is supplied to the selected word lines Sel WL connected to memory cells to be programmed, and the pass voltage VPASS of about 9 V is supplied to the unselected word lines Unsel WL connected to the memory cells not to be programmed.
After providing the program voltage to the selected word line SEL WL, a verification operation is performed to detect current flowing through the cell string in order to check whether the memory cells were programmed normally. A verification voltage Vread is provided to the selected word lines Sel WL, and the pass voltage VPASS of about 6.5 V is supplied to the unselected word line Unsel WL.
During a program operation, the pass voltage VPASS of 9V is provided to the unselected word lines Unsel WL as described above, but during the period of a verification operation, the pass voltage VPASS is lowered to 6.5 V. This is for the purpose of preventing a threshold voltage distribution of memory cells, which could rise owing to a read disturbance phenomenon occurring when the pass voltage VPASS of 9 V is supplied during the verification operation as in the program operation, from having a bad influence on the cell characteristic and distribution.
FIG. 2 shows the voltage waveforms of a pass voltage and the signals utilized in a conventional circuit for controlling the voltage level of unselected word lines in a semiconductor memory device.
In a conventional circuit, a charge pump circuit (not shown) is driven to generate a pass pump voltage (not shown), and a regulator (not shown) generates a pass voltage VPASS by using the pass pump voltage. Next, a switch (not shown) receives the pass voltage VPASS and supplies it to the unselected word lines Unsel WL.
When a semiconductor memory device switches from a program operation to a verification operation in a conventional manner, FIG. 2 shows that the unselected word lines Unsel WL are discharged to 0 V due to inactivation of the switch that performs to provide the received pass voltage VPASS to the unselected word lines Unsel WL.
In a conventional circuit, a regulator would generate a constant pass voltage VPASS by down-converting the pass pump voltage by comparing a bandgap voltage and a feedback voltage generated by feeding back the voltage level of an output node.
When the pass voltage VPASS level is normal during the program to verification operation switch, the pass voltage VPASS is discharged for a short time before it is set to a target level. However, when the pass voltage VPASS level is abnormal, the time for discharging the pass voltage VPASS becomes long, and so the switch may be activated during the time for which the pass voltage VPASS is discharged to the target level. Then, the voltage level of the unselected word line Unsel WL becomes higher than the target level, which is unstable, for a lapse of time until the unselected word lines Unsel WL reaches the target level and be stabilized. A path along which the pass voltage VPASS is discharged when a program operation switches to a verification operation includes a path to the resistor of the regulator and a path to a transistor at the output terminal of the regulator. In order to reduce the current flow of the pump pass voltage from the charge pump circuit to the resistor in the regulator, a resistor in the regulator is of a high resistance value. Then, the pass voltage VPASS is discharged through the transistor at the output terminal of the regulator. The amount of discharge current varies according to the temperature characteristic of the transistor. This leads to increased enable period of a word line discharge signal with consideration taken of the change in the amount of discharge current. In this case, the pass voltage VPASS may drop to a level lower than the target level, and restoration of the pass voltage VPASS will require undesirable current consumption and time.